This invention relates generally to integrated circuit and, in particular, to integrated circuits with floating-point arithmetic circuitry.
Programmable logic devices (PLDs) include logic circuitry such as look-up tables (LUTs) and sum-of-product based logic that are designed to allow a user to customize the circuitry to the user's particular needs. This configurable logic is typically divided into individual logic circuits that are referred to as logic elements (LEs). The LEs may be grouped together to form larger logic blocks referred to as logic array blocks (LABs) that may be configured to share the same resources (e.g., registers and memory). In addition to this configurable logic, PLDs also include programmable interconnect or routing circuitry that is used to connect the inputs and outputs of the LEs and LABs. The combination of this programmable logic and routing circuitry is referred to as soft logic.
Besides soft logic, PLDs say also include specialized processing blocks that implement specific predefined logic functions and thus cannot be configured by the user. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. Examples of structures that are commonly implemented in such specialized processing blocks include: adders, multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), logic AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block. A common application for the DSP block is to support fast Fourier transform (FFT) and similar arithmetic operations. For example, the Cooley-Tukey FFT algorithm involves recursively breaking down the (DFTs), which can then be combined using a “butterfly” computation. In the radix-2 case, where the operation receives two complex inputs and is broken down into two smaller sub-transforms, the butterfly computation requires six real addition type operations and four real multiplication operations (i.e., the ratio of addition to multiplication is 1.5). A conventional DSP block, however, includes only one multiplier and only one adder (i.e., the ratio of multipliers to adders is 1:1). As a result, the conventional DSP block is not optimized to performed FFT operations.
It is within this context that the embodiments described herein arise.